a). Field of the Invention
The present invention relates to a semiconductor memory, particularly a flash type semiconductor memory and a mask ROM type semiconductor memory.
b). Description of the Related Art
Demands for a high capacity semiconductor memory are increasing nowadays. Such demands are eminent particularly for a flash memory which can electrically erase the contents of stored data while keeping a large capacity specific to EPROM and is expected to become a substitute for a magnetic disk or other large capacity storage devices.
Like an EPROM, a flash memory writes data by injecting hot electrons into a floating gate, and erases the data by removing electric charges stored in the floating gate in the form of a tunnel current. In an erase operation, data "1" is written in all memory cells and then the data in all the cells are erased.
In a NOR type flash memory, data "0" and "1" are stored in correspondence with two threshold values HVth and LVth of an enhancement type MOS transistor. If electric charges are stored in the floating gate between the control gate and the channel, this state represents "1", whereas if not, it represents "0". Two threshold values HVth and LVth are, for example, about 7 V and 3 V.
Under the condition that 0 V is applied to the source, 1 V is applied to the drain, and 5 V is applied to the control gate, if the threshold value is high HVth, then the channel is not on, whereas if the threshold value is low LVth, then the channel is on. From this difference, data in the memory cell can be read. In a non-selected memory cell, the drain is made to be in a floating state, and the control gate is applied with 0 V.
If data "1" is to be written in a selected memory cell, the drain is applied with 6 V, and the control gate is applied with 12 V. In this case, electrons become hot electrons which tunnel through the oxide film over the channel and are injected into the floating gate to write data "1".
In an erase operation, data "1" is written in all cells, and thereafter, 0 V is applied to the control gates of all the cells and 12 V is applied to the sources, while making the drains be in a floating state. In this case, electrons stored in floating gates tunnel through oxide films to the sources.
In a memory cell array, control gates on the same row are connected to the same word line, and drains on the same column are connected to the same bit line.
Consider now that two word lines of such a flash memory are short-circuited. If an erase operation is performed in such a case, cells having a threshold value other than the predetermined value are generated. Specifically, even if 12 V is applied to one word line connected to the memory cell storing data "0", the other word line is applied with 0 V. Therefore, the voltage of the word lines cannot take a sufficiently high value, and the memory cells connected to the short-circuited word lines take an insufficient write state.
Next, 0 V and 12 V are applied to all word lines (control gates) and sources, respectively, in order to erase the contents of all cells. Electrons in the floating gates of the memory cells in the insufficient write state are taken out excessively, and the floating gates are positively charged. This is called an over erase.
If data "1" is written in a memory cell in an over erase state, an insufficient write state occurs because the initial level of the threshold value is not 0 but a positive potential (negative storage) and a sufficient voltage cannot be applied to the word line due to the short-circuiting. As described above, data cannot be written to all memory cells connected to the short-circuited word lines.
It is meaningless to use redundant cells on short-circuited word lines. Redundant cells are therefore connected to bit lines (on the column side).
If there is a memory cell in an over erase state, other cells connected to the same bit line are also unable to read data.
If a memory cell transistor has a negative threshold value because of an over erase, a current flows through the bit line even if the transistor is not selected and 0 V is applied. As a result, if a memory cell from which data is read is connected to the same bit line as such a memory cell with a negative threshold value, a current flows through the bit Line, irrespective of the threshold value of the cell.
Another approach to a redundancy operation for a flash memory is to use a redundant cell block. With this approach, a memory is divided into a plurality of blocks, and if there is a defective block, it is replaced by a redundant block. In this case, when an address decoded by an address decoder indicates the defective block, this address is translated into an address of the redundant block.
As described above, an appropriate redundancy scheme has been desired which can deal with a defect of a flash memory.
In the case of a mask ROM type semiconductor memory, data is written at the time of manufacture. Since the cell data cannot be changed after the manufacture, a yield has lowered as integration and capacity of the cell array has become high. It is therefore desired to improve the manufacturing yield.
As redundant cells for a conventional mask ROM type semiconductor memory, for example, a programmable ROM such as EPROM is additionally used in the memory cell array.
If a defective cell is found in a semiconductor memory by an operation test after manufacture, the address and data of the defective cell are written in a programmable ROM.
When an address of the defective cell is designated during a cell data read operation, the cell data written in the programmable ROM is automatically read.
A redundant cell unit of such a programmable ROM is generally larger than a mask ROM cell unit, resulting in a large chip area of the memory cell array.
Furthermore, a high voltage and a long work time is required for writing the address and data of a defective cell in the programmable ROM.
A mask ROM described in Japanese Patent Laid-open Publication No. 2-203500 enables a redundancy operation without using a programmable ROM.
This mask ROM type memory cell array has a parity unit for storing parity data representing a sum of all data of memory cells at each row.
Using the parity data, a parity check circuit generates a correction bit "1" if there is a parity error and a correction bit "0" if not. In accordance with the correction bit, a data correction circuit corrects output data.
With this method, a parity in addition to data is written. It takes time to write and check parity data for each memory cell.